1. Field of the Invention
This invention relates generally to microfabricated devices, and more particularly to three-dimensional devices fabricated in a semiconductor substrate suitable for co-fabrication with integrated circuitry.
2. Description of the Related Art
MicroElectroMechanical Systems (MEMS) often combine mechanical structures and microelectronic circuits to create integrated devices. MEMS have many useful applications such as filters, resonators, microsensors and microactuators. Examples of microsensors include inertial instruments such as accelerometers and gyroscopes, detectors for gasses such as carbon monoxide, and pressure sensors. Examples of microactuators include optical mirrors used for video displays, optical mirrors used in fiber-optic communication systems such as optical switches or multiplexors, and disk-drive head actuators used for increasing track density.
The performance of many devices such as accelerometers, gyroscopes, and closed-loop actuators may benefit from combining high-aspect-ratio structures with circuits integrated in the same substrate. Hence, a high-aspect-ratio structure etched into a single crystal silicon substrate that also contains integrated circuits is of particular interest. Of even greater interest is a process sequence that yields structures and circuits in the same substrate but does not significantly alter complex and expensive circuit fabrication processes. Such a process sequence enables cost-effective manufacture of devices comprising integrated circuits and structures on a single substrate.
Many MEMS-based devices utilize electrical circuits combined with air-gap capacitors to sense motion, or to apply electrostatic forces to a movable structure. Air-gap capacitors are often formed between sets of capacitor plates anchored to a substrate interleaved with plates attached to a movable structure. The performance of many capacitive-based MEMS improves as: 1) the overlap area of capacitor plates increases, 2) the distance between stationary and movable capacitor plates decreases, 3) the compliance of structures vary dramatically in different directions, 4) the mass of structures increases, and 5) the resistance of the material comprising mechanical structures decreases. The first through fourth of these performance issues are enhanced using high-aspect-ratio semiconductor technologies, wherein thickness or depth of fabricated structures is much larger than small lateral dimensions of features such as width of flexible beams and gaps between capacitor plates.
Commercial fabrication of high-quality, active electrical devices, including transistors, requires a substrate of single-crystal semiconducting material with a relatively high resistivity (in a range of about 5-50 Ohm-cm). Unfortunately, high-resistivity material is undesirable for electromechanical sense-elements due to, among other reasons: increased thermal noise, and slow electrical settling inherent in highly-resistive structures.
Often circuit elements are formed on an epitaxial layer of lightly-doped silicon grown on a layer of heavily doped silicon to improve the characteristics of devices formed therein, such as reduced susceptibility to latch-up. In this context, lightly- and heavily-doped silicon are discriminated by their bulk resistivity: lightly-doped silicon has a bulk resistivity above 1 Ohm-cm, and heavily-doped silicon has a bulk resistivity less than 0.1 Ohm-cm. When mechanical devices are formed into the surface of an epitaxial wafer, at least a portion of the mechanical device includes lightly-doped, or high-resistivity, silicon. Consequently, the contact resistance from the exposed surface of the epitaxy to the underlying low-resistivity material may be undesirably high.
Examples of fabrication processes that may include integrated circuits on the same substrate as mechanical structures, and in which the circuits may be formed in a lightly-doped layer formed on a heavily doped layer of silicon appear in the literature (see for example: Brosnihan, T. et al., xe2x80x9cEmbedded Interconnect and Electrical Isolation for High-Aspect-Ratio, SOI Inertial Instruments,xe2x80x9d Proc. 1997 International Conference on Solid-State Sensors and Actuators, Chicago, Ill., pp. 637-640, Jun. 16-19, 1997; Sridhar, U. et al. xe2x80x9cIsolation Process for surface micromachined sensors and actuators,xe2x80x9d iMEMS ""97 International MEMS Workshop, National University of Singapore, Singapore, December, 1997. See also: USPTO RPA Clark et al., application Ser. No. 09/322,381 Filed May 28, 1999; USPTO PPA Clark et al. application No. 60/127,973 Filed Apr. 6, 1999). These and similar processes, which include mechanical structures co-fabricated with circuits on a single substrate, are referred to herein as xe2x80x9cco-fabricated deep-MEMSxe2x80x9d or CDMEMS.
CDMEMS processes employ fabrication methods, or processing steps, that at some point provide a substrate material having exposed, filled, isolation trenches. Wafers at this step in their processing are hereby termed pre-circuit wafers (PCWs). However, none of the processes or structures in the previously-cited documents fully solves the problem of combining low-resistivity micromechanical structures with circuits on a single substrate.
The invention, roughly described, comprises methods and devices for co-fabricating electrical circuits and mechanical structures on a single substrate.
In one aspect, the invention is directed to a method of fabricating microelectromechanical systems. The method includes: providing a substrate having a device layer, photolithographically defining a region for selective doping of said device layer, doping said device layer region, thermally diffusing said dopant, forming circuits on said device layer using a substantially standard circuit technology, and etching a second set of trenches in the substrate to complete the definition of electrically isolated structural elements.
In another aspect, the invention is directed to a microfabricated device. The device includes a substrate having a device layer and filled, isolating trenches; a doped region of material formed by photolithographically defining a region for selective doping of said device layer, selectively doping said region, and thermally diffusing said dopant; circuits on said device layer formed using a substantially standard circuit technology; and a second set of trenches in the substrate that complete the definition of electrically isolated structural elements.
The invention is advantageous because the invention enables low-resistance mechanical structures to be co-fabricated into the same substrate on which active semiconductor devices, such as transistors, are formed. The invention provides for easy and accurate alignment of sinker diffusion to areas where structures and circuits are subsequently formed. Depending on circuit technology specificities, the invention may reduce structural resistance by up to several orders of magnitude while requiring minimal modification of circuit processing. The invention improves performance of a large class of sensors and actuators. Furthermore, the benefits of the invention may be attained using a minimal number of processing steps.